1. Field of the Invention
The present invention relates to a circuit to characterize the matching of electronic components. More particularly, the present invention relates to a circuit to characterize the matching of energy-storage components.
2. Description of the Related Art
In a mixed mode circuit design, the matching between neighboring devices is very important. Using capacitors as an example, measuring the matching condition between two neighboring capacitors can provide the circuit designers with important information in terms of circuit design. However, the accuracy of most capacitance measuring meters is often too low to obtain a precise capacitance value for assessing the degree of matching between two capacitors.
FIG. 1 is a circuit diagram showing a conventional circuit for characterizing the matching of capacitors. The circuit 10 comprises a PMOS transistor 11 and a current supply 13. The first source/drain terminal of the PMOS transistor 11 is electrically connected to the current supply 13 and the output voltage Vout. Two capacitors to be measured are a first capacitor 91 and a second capacitor 93. A second terminal of the first capacitor 91 is electrically connected to a first terminal of the second capacitor 93 and a gate terminal of the PMOS transistor 11.
If the first terminal of the first capacitor 91 is P1 and the second terminal of the capacitor 93 is P3, the conventional method is to connect P3 of the second capacitor 93 to a ground and to connect P1 of the first capacitor 91 to an input voltage Vina to produce an output voltage Vouta. Here, assuming that the first capacitor 91 has a capacitance C1 and the second capacitor 93 has a capacitance C3, then the relationship between the input voltage Vina and the output voltage Vouta can be given by the following formula:Vouta=Vina×C1/(C1+C3+Cpar)  (1).
Similarly, if the P1 terminal of the first capacitor 91 is electrically connected to the input voltage Vinb to produce a corresponding output voltage Voutb, then the relationship between the input voltage Vinb and the output voltage Voutb can be given by the following formula:Voutb=Vinb×C1/(C1+C3+Cpar)  (2).
FIG. 2 is a graph showing the functional relationship between the input voltage Vin and the output voltage Vout. As shown in FIG. 2, the straight line 21 shows the functional relationship between the input voltage Vin and the output voltage Vout and the value of the slope S1 can be represented using the following formula:
S1=(Voutb−Vouta)/(Vinb−Vina), and according to formulae (1) and (2), the above formula can be given by:
S1=C1/(C1+C3+Cpar) (3), wherein Cpar is the parasitic capacitance of the conventional circuit 10.
Thereafter, the terminal P1 of the first capacitor 91 is connected to a ground and the terminal P3 of the second capacitor 93 is electrically connected to a dc input voltage Vin. Similarly, the slope S2 (the slope of the straight line 22) of the functional relationship between the input voltage and the output voltage can be obtained from the following formula:S2=C3/(C1+C3+Cpar)  (4).
After some operation of formulae (3) and (4), the following formula is obtained:2×(S1−S2)/(S1+S2)=2×(C1−C2)/(C1+C2)  (5).
According to formula (5), if the two slopes S1 and S2 of the functional relation between the input voltage and the output voltage are obtained, the degree of matching between the first capacitor 91 and the second capacitor 93 can be computed.
However, the conventional method has the following disadvantages.
1. If the capacitors to be measured have a large capacitance or are inter-digital capacitors, the PMOS transistor can be easily damaged due to the antenna effect, such that the measurement cannot be achieved.
2. The PMOS transistor can have a variety of designs or specifications so that the testing conditions need to be changed constantly. In other words, the person taking the measurement must set up a new set of testing conditions to reflect the design and specification of the PMOS transistor. Thus, the measuring process is complicated and cumbersome.
3. As shown in FIG. 3, which is a graph showing the functional relationship between the input voltage and the output voltage for matching different capacitors with different sizes of capacitance using a conventional circuit, the shape of the function differs for each capacitance value. Furthermore, the PMOS transistor is a non-linear device so that only a portion of the graph has a linear characteristic. If the area for getting the slope lies in a non-linear region, an accurate result cannot be obtained.